Bumped circuit wafers are known.
Applicant's earlier patents directed to semiconductor device manufacturing processes include:
U.S. Pat. No. 6,013,534 to Mountain, entitled “Method of Thinning Integrated Circuits Received in Die Form”, issued Jan. 11, 2000, which is incorporated herein by reference; and
U.S. Pat. No. 6,017,822 to Mountain, entitled “Method of Thinning Semiconducted Wafer of Smaller Diameter than Thinning Equipment Was Designed For”, issued Jan. 25, 2000, and which is incorporated herein by reference.
Additional known United States patent documents include:
U.S. Pat. No. 6,506,681 to Grigg et al.;
U.S. Pat. No. 6,716,665 B2 to Baba et al.;
U.S. Pat. No. 6,419,148 B1 to Waxler et al.;
U.S. Pat. No. 3,753,238 to Tutelman; and
U.S. Pat. No. 6,610,559 B2 to Wang et al.
A known Japanese patent document is:
JP 56 60025 to Iguchi Shigeki, published May 23, 1981, and entitled “Bonding Method for Semiconductor Element”.
Additional known U.S. patents include:
U.S. Pat. No. 5,691,245 to Bakhit et al.;
U.S. Pat. No. 5,817,541 to Averkiou;
U.S. Pat. No. 5,998,291 to Bakhit et al.;
U.S. Pat. No. 6,291,877 to Usami et al.;
U.S. Pat. No. 6,365,974 B1 to Abbott et al.;
U.S. Pat. No. 6,228,686 B1 to Smith et al.;
U.S. Pat. No. 6,627,998 B1 to Caletka et al.; and
U.S. Pat. No. 6,653,742 B1 to Lin.
A history of wafer-level packaging (WLP) is set forth in an article entitled “Wafer-Level Packaging Today”, Goodman, T. et al., Circuits Assembly, February 2004, pages 28–32, www.circuitsassembly.com, and which is incorporated herein by references.
Known chip scale packages (CSP) are being used today instead of the larger large area packages used previously. The densest assemblies are those using flip-chip technology in order to place the CSP directly on a substrate. This technique is termed direct chip attached (DCA) technology. Densifying assemblies in this manner has been advantageously used in portable electronic devices.
Another known technology for densifying assemblies is the thinning of semiconductor devices.
Known techniques of thinning devices have been unsuited to fabricate both high yield and high reliability solder bumps. If semiconductor devices are thinned before a bumping step, known wafers are fragile and break easily during the bumping process. If semiconductor devices are thinned after bumping, the topography of the bumped wafer (e.g. height variations owing to the bumps) has made it difficult to produce wafers sufficiently thin to satisfy the requirements of extremely thin wafers.
U.S. Pat. No. 6,506,681 to Grigg et al. set forth above has described a method of making flip-chip assemblies which are thinned after bumping; however, that patent discloses a limitation when thinning prior to bumping of 250 microns, owing to the handling requirements for the bumping process that limit wafer thinness under traditional grinding methods.
Known techniques have likewise failed to keep up with the demand for compact, low profile applications, such as in the portable electronic market for pagers, cellular telephones, and the like. Each of those applications demands low profile packages. These demands severely constrain packaging parameters.
A currently known standard of bumping wafers includes providing solder bumps on the conductive layer on a chip. However, if the initial silicon substrate is too thin, it has been difficult to handle during processing without unacceptable die breakage levels.
When the conventional silicon substrate is sufficiently thick to reduce handling and breakage problems, there is a trade-off between reducing the chip scale package thickness and reducing breakage problems.
There is thus a need for a method of fabricating bumped thin circuit wafers that overcomes the drawbacks of the prior art.
It can be seen that there likewise is a need for a method of providing thinned bumped wafers that are thinner than known semiconductor devices.